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fxl2sd106 ? low-voltage dual-s upply 6-bit voltage translator with auto-det ection sensing ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 june 2011 fxl2sd106 low-voltage dual-supply 6-bit voltage translator with auto-direction sensing features ? bi-directional interface between two levels: 1.1v and 3.6v ? fully configurable: inputs and outputs track v cc level ? non-preferential power-up; either v cc may be powered-up first ? outputs remain in 3-state until active v cc level is reached ? outputs switch to 3-state if either v cc is at gnd ? power-off protection ? bus hold on data inputs eliminates need for pull- up resistors (do not use resistors on the a or b ports) ? oe and clk in are referenced to v cca voltage ? packaged in 16-terminal dqfn (2.5mm x 3.5mm) ? direction control not needed ? 80 mbps throughput translating between 1.8v and 2.5v ? esd protection exceeds: ? 12kv hbm (b port i/o to gnd) (per jesd22-a114 & mil std 883e 3015.7) ? 8kv hbm (a port i/o to gnd) (per jesd22-a114 & mil std 883e 3015.7) ? 1kv cdm (per esd stm 5.3) general description the fxl2sd106 is a configurable dual-voltage-supply translator designed for both uni-directional and bi- directional voltage translation between two logic levels. the device allows translation between voltages as high as 3.6v to as low as 1.1v. the a port tracks the v cca level and the b port tracks the v ccb level. this allows for bi-directional voltage translatio n over a variety of voltage levels: 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v. the device remains in 3-state until both v cc reach active levels, allowing either v cc to be powered-up first. inter- nal power-down control circuits place the device in 3- state if either v cc is removed. the oe input, when low, disables both a and b ports by placing them in a 3-stat e condition. the fxl2sd106 is designed so that oe and clk in are supplied by v cca . the device senses an input signal on a or b port auto- matically. the input signal is transferred to the other port. the fxl2sd106 is not designed for sd card applica- tions. the internal bus hold circuitry conflicts with pull-up resistors. sd cards have intern al pull-up resistors on the cd/dat3 pins. ordering information order number package number package description fxl2sd106bqx mlp16e 16-terminal depopulated quad very-thin flat pack, no leads (dqfn), jedec mo-241, 2.5mm x 3.5mm
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 2 fxl2sd106 ? low-voltage dual-s upply 6-bit votlage translator with auto-direction sensing connection diagram pin description functional diagram function table power-up/power-down sequencing fxl translators offer an advantage in that either v cc may be powered up first. this benefit derives from the chip design. when either v cc is at 0 volts, outputs are in a high-impedance state. th e control input (oe) is designed to track the v cca supply. a pull-down resistor tying oe to gnd should be used to ensure that bus con- tention, excessive currents, or oscillations do not occur during power-up / power-down. the size of the pull-down resistor is based upon the current-sinking capability of the device driving the oe pin. the recommended power-up sequence is the following: 1. apply power to the first v cc . 2. apply power to the second v cc . 3. drive the oe input high to enable the device. the recommended power-down sequence is the following: 1. drive oe input low to disable the device. 2. remove power from either v cc . 3. remove power from other v cc . number name description 1v cca a-side power supply 2 clk in a-side input 3?7 a 0 ?a 4 a-side inputs or 3-state outputs 8 oe output enable input 9 gnd ground 10?14 b 4 ?b 0 b-side inputs or 3-state outputs 15 clk out 3-state output 16 v ccb b-side power supply 2 3 4 5 6 7 15 14 13 12 11 10 1 16 8 9 clk in a 0 a 1 a 2 a 3 a 4 b 0 b 1 b 2 b 3 b 4 clk out vccb vcca oe gnd control outputs oe low logic level 3-state high logic level normal operation oe b0 ? b4 a0 ? a4 vcca vccb clk out clk in
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 3 fxl2sd106 ? low-voltage dual-s upply 6-bit voltagetranslator with auto-direction sensing absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. note: 1. i o absolute maximum ra ting must be observed. recommended oper ating conditions (2) the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal perfor mance to the datasheet specif ications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 2. all unused inputs and i/o pins must be held at v cci or gnd. symbol parameter rating v cca , v ccb supply voltage ?0.5v to +4.6v v i dc input voltage i/o port a i/o port b oe, clk in ?0.5v to +4.6v ?0.5v to +4.6v ?0.5v to +4.6v v o output voltage (1) outputs 3-state outputs active (a n ) outputs active (b n , clk out) ?0.5v to +4.6v ?0.5v to v cca + 0.5v ?0.5v to v ccb + 0.5v i ik dc input diode current at v i ? 0v ?50ma i ok dc output diode current at v o ? 0v v o ? v cc ?50ma +50ma i oh / i ol dc output source/sink current ?50ma / +50ma i cc dc v cc or ground current per supply pin 100ma t stg storage temperature range ?65c to +150c symbol parameter rating v cca or v ccb power supply operating 1.1v to 3.6v input voltage port a port b oe, clk in 0.0v to 3.6v 0.0v to 3.6v 0.0v to v cca dynamic output current in i oh /i ol with v cc at 3.0v to 3.6v 2.3v to 2.7v 1.65v to 1.95v 1.4v to 1.65v 1.1v to 1.4v 18.0ma 11.8ma 7.4ma 5.0ma 2.6ma static output current i oh /i ol with v cc at 1.1v to 3.6v 20.0a t a free air operating temp erature ?40c to +85c ? t / ? v maximum input edge rate v cca/b ? 1.1v to 3.6v 10ns/v
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 4 fxl2sd106 ? low-voltage dual-s upply 6-bit votlage translator with auto-direction sensing dc electrical characteristics (t a = ?40c to +85c) symbol parameter v cca (v) v ccb (v) conditions min. typ. max. units v ih high level input voltage 1.4?3.6 1.1?3.6 data inputs a n , clk in, oe 0.6 x v cca v 1.1?1.4 1.1?3.6 0.9 x v cca 1.1?3.6 1.4?3.6 data inputs b n 0.6 x v ccb 1.1?3.6 1.1?1.4 0.9 x v ccb v il low level input voltage 1.4?3.6 1.1?3.6 data inputs a n , clk in, oe 0.35 x v cca v 1.1 ?1.4 1.1?3.6 0.1 x v cca 1.1?3.6 1.4?3.6 data inputs b n 0.35 x v ccb 1.1?3.6 1.1?1.4 0.1 x v ccb v oh (3) high level output voltage 1.65?3.6 1.1?3.6 data outputs a n , i hold = ?20a 0.75 x v cca v 1.1?1.4 1.1?3.6 0.8 1.1?3.6 1.65?3.6 data outputs b n , i hold = ?20a 0.75 x v ccb 1.1?3.6 1.1?1.4 0.8 v ol (3) low level output voltage 1.65?3.6 1.1?3.6 data outputs a n , i hold = 20a 0.2 x v cca v 1.1?1.4 1.1?3.6 0.3 1.1?3.6 1.65?3.6 data outputs b n , i hold = 20a 0.2 x v ccb 1.1?3.6 1.1?1.4 0.3 i i(odh) (4) bushold input overdrive high current 3.6 3.6 data inputs a n , b n 450 a 2.7 2.7 300 1.95 1.95 200 1.6 1.6 120 1.4 1.4 80 i i(odl) (5) bushold input overdrive low current 3.6 3.6 data inputs a n , b n -450 a 2.7 2.7 -300 1.95 1.95 -200 1.6 1.6 -120 1.4 1.4 -80 i i input leakage current 1.1?3.6 3.6 oe, clk in, v i = v cca or gnd 1.0 a i off power off leakage current 03.6a n , v o = 0v to 3.6v 2.0 a 3.6 0 b n , clk out, v o = 0v to 3.6v 2.0 i oz (6) 3-state output leakage 3.6 3.6 a n , b n , clk out, v o = 0v or 3.6v, oe = v il 2.0 a 3.6 0 a n , v o = 0v or 3.6v, oe = don?t care 2.0 03.6b n , clk out, v o = 0v or 3.6v, oe = don?t care 2.0 i cca/b (7)(8) quiescent supply current 1.1?3.6 1.1?3.6 v i = v cci or gnd, i o = 0 5.0 a i ccz (7) quiescent supply current 1.1?3.6 1.1?3.6 v i = v cci or gnd, i o = 0, oe = v il 5.0 a i cca (7) quiescent supply current 0 1.1?3.6 v i = v ccb or gnd; i o = 0 -2.0 a 1.1?3.6 0 v i = v cca or gnd; i o = 0 2.0
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 5 fxl2sd106 ? low-voltage dual-s upply 6-bit votlage translator with auto-direction sensing notes: 3. this is the output voltage for static conditions. dynamic dr ive specifications are given in ?dynamic output electrical characteristics.? 4. an external driver must source at least the specified current to switch low-to-high. 5. an external driver must source at least the specified current to switch high-to-low. 6. ?don?t care? indicates any valid logic level. 7. v cci is the v cc associated with the input side. 8. reflects current per supply, v cca or v ccb . dynamic output elect rical characteristics (9) a port (a n ) output load: c l = 15pf, r l ? 1m ? b port (b n , clk out) output load: c l = 15pf, r l ? 1m ? notes: 9. dynamic output characteristi cs are guaranteed, but not tested. 10. see figure 5. 11. see figure 6. i ccb (7) quiescent supply current 1.1?3.6 0 vi = v ccb or gnd; io = 0 -2.0 a 0 1.1?3.6 vi = v cca or gnd; io = 0 2.0 symbol parameter t a = -40c to +85c, v cca = units 3.0v to 3.6v 2.3v to 2.7v 1.65v to 1.95v 1.4v to 1.6v 1.1v to 1.3v typ. max. typ. max. typ. max. typ. max. typ. t rise (10) output rise time a port 3.0 3.5 4.0 5.0 7.5 ns t fall (11) output fall time a port 3.0 3.5 4.0 5.0 7.5 ns i ohd (10) dynamic output current high -18.0 -11.8 -7.4 -5.0 -2.6 ma i old (11) dynamic output current low +18.0 +11.8 +7.4 +5.0 +2.6 ma symbol parameter t a = -40c to +85c, v ccb = units 3.0v to 3.6v 2.3v to 2.7v 1.65v to 1.95v 1.4v to 1.6v 1.1v to 1.3v typ. max. typ. max. typ. max. typ. max. typ. t rise (10) output rise time b port 3.0 3.5 4.0 5.0 7.5 ns t fall (11) output fall time b port 3.0 3.5 4.0 5.0 7.5 ns i ohd (10) dynamic output current high -18.0 -11.8 -7.4 -5.0 -2.6 ma i old (11) dynamic output current low +18.0 +11.8 +7.4 +5.0 +2.6 ma dc electrical characteristics (t a = ?40c to +85c) (continued) symbol parameter v cca (v) v ccb (v) conditions min. typ. max. units
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 6 fxl2sd106 ? low-voltage dual-s upply 6-bit voltagetranslator with auto-direction sensing ac characteristics v cca = 3.0v to 3.6v v cca = 2.3v to 2.7v v cca = 1.65v to 1.95v v cca = 1.4v to 1.6v note: 12. skew is the variation of propagation delay between output signals and applies only to output signals on the same port (a n or b n ) and switching with the same polarity ( low-to-high or high-to-low). see figure 8. symbol parameter t a = -40c to +85c, v ccb = units 3.0v?3.6v 2.3v?2.7v 1.65v?1. 95v 1.4v?1.6v 1.1v?1.3v min. max. min. max. mi n. max. min. max. typ. t plh , t phl a to b 0.2 3.5 0.3 3.9 0.5 5.4 0.6 6.8 22.0 ns b to a 0.2 3.5 0.2 3.8 0.3 5.0 0.5 6.0 15.0 ns t plh , t phl clk in to clk out 3.0 3.5 4.5 6.0 15.0 ns t pzl , t pzh oe to a, oe to b 1.7 1.7 1.7 1.7 1.7 s t skew (12) a port, b port 0.5 0.5 0.5 1.0 1.0 ns symbol parameter t a = -40c to +85c, v ccb = units 3.0v?3.6v 2.3v?2.7v 1.65v?1. 95v 1.4v?1.6v 1.1v?1.3v min. max. min. max. mi n. max. min. max. typ. t plh , t phl a to b 0.2 3.8 0.4 4.2 0.5 5.6 0.8 6.9 22.0 ns b to a 0.3 3.9 0.4 4.2 0.5 5.5 0.5 6.5 15.0 ns t plh , t phl clk in to clk out 3.5 4.0 4.5 6.5 15.0 ns t pzl , t pzh oe to a, oe to b 1.7 1.7 1.7 1.7 1.7 s t skew (12) a port, b port 0.5 0.5 0.5 1.0 1.0 ns symbol parameter t a = -40c to +85c, v ccb = units 3.0v?3.6v 2.3v?2.7v 1.65v?1. 95v 1.4v?1.6v 1.1v?1.3v min. max. min. max. mi n. max. min. max. typ. t plh , t phl a to b 0.3 5.0 0.5 5.5 0.8 6.7 0.9 7.5 22.0 ns b to a 0.5 5.4 0.5 5.6 0.8 6.7 1.0 7.0 15.0 ns t plh , t phl clk in to clk out 4.5 4.5 6.3 6.7 15.0 ns t pzl , t pzh oe to a, oe to b 1.7 1.7 1.7 1.7 1.7 s t skew (12) a port, b port 0.5 0.5 0.5 1.0 1.0 ns symbol parameter t a = -40c to +85c, v ccb = units 3.0v?3.6v 2.3v?2.7v 1.65v?1. 95v 1.4v?1.6v 1.1v?1.3v min. max. min. max. mi n. max. min. max. typ. t plh , t phl a to b 0.5 6.0 0.5 6.5 1.0 7.0 1.0 8.5 22.0 ns b to a 0.6 6.8 0.8 6.9 0.9 7.5 1.0 8.5 15.0 ns t plh , t phl clk in to clk out 6.0 6.5 6.7 8.5 15.0 ns t pzl , t pzh oe to a, oe to b 1.7 1.7 1.7 1.7 1.7 s t skew (12) a port, b port 1.0 1.0 1.0 1.0 1.0 ns
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 7 fxl2sd106 ? low-voltage dual-s upply 6-bit votlage translator with auto-direction sensing maximum data rate (13)(14) note: 13. maximum data rate is guaranteed but not tested. 14. maximum data rate is specified in megabits per second. see figure 7. it is equivale nt to two times the f-toggle frequency, specified in megahertz. for exam ple, 100 mbps is equivalent to 50 mhz. capacitance v cca t a = -40c to +85c, v ccb = units 3.0v to 3.6v 2.3v to 2.7v 1.65v to 1.95v 1.4v to 1.6v 1.1v to 1.3v min. min. min. min. typ. v cca = 3.0v to 3.6v 100 100 80 60 20 mbps v cca = 2.3v to 2.7v 100 100 80 60 20 mbps v cca =1.65v to 1.95v 80 80 60 40 20 mbps v cca = 1.4v to 1.6v 60 60 40 40 20 mbps typ. typ. typ. typ. typ. v cca = 1.1v to 1.3v 20 20 20 20 20 mbps symbol parameter conditions t a = +25c units typical c in input capacitance, oe, clk in vcca = vccb = gnd 4pf c i/o input/output capacitance a n vcca = vccb = 3.3v, oe = vcca 5pf b n , clk out 6 c pd power dissipation capacitance vcca = vccb = 3.3v, vi = 0v or vcc, f = 10mhz 25 pf
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 8 fxl2sd106 ? low-voltage dual-s upply 6-bit votlage translator with auto-direction sensing figure 1. ac test circuit ac load table test input signal output enable control t plh , t phl data pulses v cca t pzl 0v low to high switch t pzh v cci low to high switch v cco cl rl 1.2v 0.1v 15pf 1m ? 1.5v 0.1v 15pf 1m ? 1.8v 0.15v 15pf 1m ? 2.5v 0.2v 15pf 1m ? 3.3 0.3v 15pf 1m ? v cc dut c1 r1 test signal
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 9 fxl2sd106 ? low-voltage dual-s upply 6-bit voltagetranslator with auto-direction sensing input t r = t f = 2.0ns, 10% to 90% input t r = t f = 2.5ns, 10% to 90%, @ vi = 3.0v to 3.6v only figure 2. waveform for inverting and non-inverting functions input t r = t f = 2.0ns, 10% to 90% input t r = t f = 2.5ns, 10% to 90%, @ vi = 3.0v to 3.6v only figure 3. 3-state output low enable time for low voltage logic v cci v cco gnd data in data out t pxx t pxx v mi v mo data out output control t pzl v mi v cca v ol gnd v y input t r = t f = 2.0ns, 10% to 90% input t r = t f = 2.5ns, 10% to 90%, @ vi = 3.0v to 3.6v only figure 4. 3-state output high enable time for low voltage logic note: 15. v cci = v cca for control pin oe or vmi = (v cca / 2). data out output control t pzh v mi v cca v oh gnd v x symbol vcc vmi (15) v cci / 2 vmo v cco / 2 vx 0.9 x v cco vy 0.1 x v cco figure 7. maximum data rate figure 8. output skew time v cci v cci /2 v cci /2 gnd data in t w max. data rate, f = 1/t w v cco v mo t skew t skew v mo gnd data output t skew = (t phlmax ? t phlmin ) or (t plhmax ? t plhmin ) v cco v mo v mo gnd data output figure 5. active output rise time and dynamic output current high figure 6. active output fall time and dynamic output current low t rise 80% x v cco 20% x v cco i ohd (c l + c i/o ) x = (c l + c i/o ) x v out t v oh v ol v out time (20% ? 80%) x v cco t rise t fall 80% x v cco 20% x v cco v ol v oh v out time i old (c l + c i/o ) x = (c l + c i/o ) x v out t (80% ? 20%) x v cco t fall
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 10 fxl2sd106 ? low-voltage dual-s upply 6-bit voltagetranslator with auto-direction sensing physical dimensions figure 9. 16-terminal depopulated quad, very-thin flat pack, no leads (dqfn), jedec mo-241 2.5mm x 3.5mm package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ for current tape and reel specifications, vi sit fairchild semiconduc tor?s packaging area: http://www.fairchildsemi.com/ms/ms/ms-522.pdf
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fxl2sd106 ? rev. 1.8.1 11 fxl2sd106 ? low-voltage dual-s upply 6-bit voltage translator with auto-dir ection sensing

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